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74AUP1T50 Datasheet Low-power Buffer

Manufacturer: Nexperia

Overview: 74AUP1T50 Low-power buffer with voltage-level translator Rev. 4 — 5 August 2022 Product data sheet 1.

General Description

The 74AUP1T50 provides the single buffer function.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V.

The 74AUP1T50 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply voltage.

Key Features

  • Wide supply voltage range from 2.3 V to 3.6 V.
  • High noise immunity.
  • ESD protection:.
  • HBM JESD22-A114F Class 3A exceeds 5000 V.
  • CDM JESD22-C101E exceeds 1000 V.
  • Low static power consumption; ICC = 1.5 μA (maximum).
  • Latch-up performance exceeds 100 mA per JESD 78 Class II.
  • Inputs accept voltages up to 3.6 V.
  • Low noise overshoot and undershoot < 10 % of VCC.
  • IOFF circuitry provides partial power-down mode ope.

More Datasheets from Nexperia

Part Number Description
74AUP1T57 Low-power configurable gate
74AUP1T58 Low-power configurable gate
74AUP1T00 Low-power 2-input NAND gate
74AUP1T02 Low-power 2-input NOR gate
74AUP1T04 Low-power inverter
74AUP1T08 Low-power 2-input AND gate
74AUP1T14 Low-power inverter
74AUP1T17 Low-power buffer
74AUP1T32 Low-power 2-input OR-gate
74AUP1T34 Low-power dual supply translating buffer

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