Description
The 74HC138-Q100; 74HCT138-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7).
Features
- Automotive product qualification in accordance with AEC-Q100 (Grade 1).
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
- Wide supply voltage range from 2.0 to 6.0 V.
- CMOS low power dissipation.
- High noise immunity.
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
- Demultiplexing capability.
- Multiple input enable for easy expansion.
- Ideal for memory chip select decoding.
- Active LO.
74HC138-Q100 Datasheet
