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74HCS16507-Q100
8-bit parallel-load shift register with Schmitt-trigger inputs
and open-drain outputs
Rev. 1 — 5 June 2025
Product data sheet
1. General description
The 74HCS16507-Q100 is an 8-bit serial or parallel-in/serial-out shift register with open-drain outputs. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-toHIGH transitions of the CP input. A HIGH on CE will disable the CP input. Inputs include clamp diodes.
74HCS16507-Q100 Datasheet
