74HCT594-Q100 Datasheet | Nexperia

74HC594-Q100; 74HCT594-Q100 8-bit shift register with output register Rev. 2 - 13 June 2016 Product data sheet 1. General description The 74HC594-Q100; 74HCT594-Q100 is a high-speed Si-gate CMOS device and is pin patible with Low-Power Schottky TTL (LSTTL). The 74HC594-Q100; 74HCT594-Q100 is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct overriding clears (SHR and STR) are provided on both the shift and storage registers. A serial output (Q7S) is provided for cascading purposes. Both the shift and storage register clocks are positive-edge triggered. If both clocks are connected together, the shift register is always one count pulse ahead of the storage register. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits - Automotive product qualification in accordance with AEC-Q100 (Grade 1) - Specified from - 40 C to +85 C and from - 40 C to +125 C - Synchronous serial input and output - plies with JEDEC standard No.7A - 8-bit parallel output - Shift and storage registers have independent direct clear and clocks - Independent clocks for shift and storage registers - 100 MHz (typical) - ESD protection: - MIL-STD-883, method 3015 exceeds 2000 V - HBM JESD22-A114F exceeds 2000 V - MM JESD22-A115-A exceeds 200 V (C = 200 p F, R = 0 ) 3. Applications - Serial-to parallel data conversion - Remote control holding register Nexperia 74HC594-Q100;...