74HCT594D Datasheet | Nexperia

74HC594; 74HCT594 8-bit shift register with output register Rev. 7 - 20 October 2022 Product data sheet 1. General description The 74HC594; 74HCT594 is an 8-bit serial-in/serial or parallel-out shift register with a storage register. Separate clock and reset inputs are provided on both shift and storage registers. The device Features a serial input (DS) and a serial output (Q7S) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the SHCP input, and the data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. A LOW level on one of the two register reset pins (SHR and STR) will clear the corresponding register. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits - Synchronous serial input and output - 8-bit parallel output - Shift and storage registers have independent direct clear and clocks - Independent clocks for shift and storage registers - 100 MHz (typical) - Wide supply voltage range from 2.0 V to 6.0 V - CMOS low power dissipation - High noise immunity - Latch-up performance exceeds 100 m A per JESD 78 Class II Level B - Input levels: - For 74HC594: CMOS level - For 74HCT594: TTL level - plies with JEDEC standards - JESD8C (2.7 V to 3.6 V) - JESD7A (2.0 V to 6.0 V) - ESD protection: - HBM JESD22-A114F exceeds 2 k V - MM JESD22-A115-A exceeds 200 V (C = 200 p F, R = 0 Ω) - Multiple package options - Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Applications - Serial-to parallel data...