74LV165A-Q100 Datasheet PDF - nexperia 8-bit parallel-in/serial-out shift register Specs

74LV165A-Q100 - 8-bit parallel-in/serial-out shift register

Datasheet Summary

Description

The 74LV165A-Q100 is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last stage.

When the parallel-load input (PL) is LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously.

Features

Automotive product qualification in accordance with AEC-Q100 (Grade 3).
Specified from 40 C to +85 C.
Wide supply voltage range from 2.0 V to 5.5 V.
Synchronous parallel-to-serial.

Datasheet Details

Part number	74LV165A-Q100
Manufacturer	nexperia
File Size	773.88 KB
Description	8-bit parallel-in/serial-out shift register
Datasheet	74LV165A-Q100 Datasheet
Additional preview pages of the 74LV165A-Q100 datasheet.

📁 Similar Datasheet

74LV165 - 8-bit parallel-in/serial-out shift register (Philips)

74LV161 - Presettable synchronous 4-bit binary counter (Philips)

74LV163 - Presettable synchronous 4-bit binary counter (Philips)

74LV164 - 8-bit serial-in/parallel-out shift register (Philips)

74LV10 - Triple 3-input NAND gate (Philips)

74LV107 - Dual JK flip-flop (Philips)

74LV109 - Dual JK flip-flop (Philips)

74LV11 - Triple 3-input AND gate (Philips)

74LV123 - Dual retriggerable monostable multivibrator (Philips)

74LV125 - Quad buffer/line driver (Philips)

Full PDF Text Transcription

Click to expand full text

74LV165A-Q100 8-bit parallel-in/serial-out shift register Rev. 3 — 28 March 2014 Product data sheet 1. General description The 74LV165A-Q100 is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel-load input (PL) is LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously. When input PL is HIGH, data enters the register serially at the input DS. It shifts one place to the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the succeeding stage.

Published: Jul 29, 2019 |