74LV74 Datasheet | Nexperia

description The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (n D), clock (n CP), set (n SD) and reset (n RD) inputs, and plementary n Q and n Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the n Q output. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. 2. Features and benefits - Wide supply voltage range from 1.0 V to 5.5 V - Optimized for low voltage applications from 1.0 V to 3.6 V - CMOS low power dissipation - Latch-up performance exceeds 100 m A per JESD 78 Class II Level B - Direct interface with TTL levels (2.7 V to 3.6 V) - ESD protection: - HBM JESD22-A114F exceeds 2000 V - MM JESD22-A115-A exceeds 200 V - Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74LV74D -40 °C to +125 °C 74LV74PW -40 °C to +125 °C Name Description Version SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 4. Functional diagram 4 10 1SD 2SD 2 12 1D 2D 1Q 2Q 5 9 3 1CP CP 11 2CP Q 1Q...