The 74LV74 is a Dual D-type flip-flop.
| Package | SOP |
|---|---|
| Mount Type | Surface Mount |
| Pins | 14 |
| Operating Voltage | 3.3 V |
| Max Voltage (typical range) | 5.5 V |
| Min Voltage (typical range) | 1 V |
| Logic Function | AND, D-Type, Flip-Flop |
| Clock Edge Trigger | Positive Edge |
| Part Number | 74LV74 Datasheet |
|---|---|
| Manufacturer | Philips Semiconductors |
| Overview |
The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. The 74LV74 is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, cloc.
* Wide operating voltage: 1.0 to 5.5V * Optimized for Low Voltage applications: 1.0 to 3.6V * Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V * Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V, * Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V, * Output capability: standard. |
| Part Number | 74LV74 Datasheet |
|---|---|
| Description | Dual D-type flip-flop |
| Manufacturer | Nexperia |
| Overview |
The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that me.
and benefits
* Wide supply voltage range from 1.0 V to 5.5 V * Optimized for low voltage applications from 1.0 V to 3.6 V * CMOS low power dissipation * Latch-up performance exceeds 100 mA per JESD 78 Class II Level B * Direct interface with TTL levels (2.7 V to 3.6 V) * ESD protection: * HBM JESD22. |
| Seller | Inventory | Price Breaks | Buy |
|---|---|---|---|
| Verical | 12280 | 1269+ : 0.2956 USD 10000+ : 0.2636 USD 100000+ : 0.2209 USD |
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| Verical | 6840 | 1269+ : 0.2956 USD 10000+ : 0.2636 USD 100000+ : 0.2209 USD |
View Offer |
| Verical | 3420 | 1269+ : 0.2956 USD 10000+ : 0.2636 USD 100000+ : 0.2209 USD |
View Offer |
| Part Number | Manufacturer | Description |
|---|---|---|
| 74LV74-Q100 | Nexperia | Dual D-type flip-flop |
| 74LV74D | Nexperia | Dual D-type flip-flop |