Datasheet Summary
74VHC125; 74VHCT125
Quad buffer/line driver; 3-state
Rev. 3
- 8 April 2020
Product data sheet
1. General description
The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin patible with Low-power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard JESD7-A.
The 74VHC125; 74VHCT125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state.
The 74VHC125; 74VHCT125 are identical to the 74VHC126; 74VHCT126 but have active LOW enable inputs.
2. Features and benefits
- Balanced propagation delays
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