74VHC125 Description
74VHCT125 are high-speed Si-gate CMOS devices and are pin patible with Low-power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard JESD7-A. 74VHCT125 provides four non-inverting buffer/line drivers with 3-state outputs.
74VHC125 Key Features
- Balanced propagation delays
- All inputs have a Schmitt-trigger action
- Inputs accepts voltages higher than VCC
- Input levels
- The 74VHC125 operates with CMOS logic levels
- The 74VHCT125 operates with TTL logic levels
- ESD protection
- HBM JESD22-A114E exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
- CDM JESD22-C101C exceeds 1000 V