74VHC126 Description
74VHCT126 are high-speed Si-gate CMOS devices and are pin patible with Low-power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard No. 74VHCT126 provide four non-inverting buffer/line drivers with 3-state outputs.
74VHC126 Key Features
- Balanced propagation delays
- All inputs have Schmitt-trigger action
- Inputs accept voltages higher than VCC
- Input levels
- The 74VHC126 operates with CMOS input level
- The 74VHCT126 operates with TTL input level
- ESD protection
- HBM JESD22-A114E exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
- CDM JESD22-C101C exceeds 1000 V