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HEF4020B-Q100 - 14-stage binary counter

General Description

The HEF4020B is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13).

The counter advances on the HIGH-to-LOW transition of CP.

Key Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 3).
  • Specified from -40 °C to +85 °C.
  • Wide supply voltage range from 3.0 V to 15.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • High speed operation.
  • Fully static operation.
  • 5 V, 10 V, and 15 V parametric ratings.
  • Standardized symmetrical output characteristics.
  • ESD protection:.
  • MIL-STD-883, method 3015 exceeds 2000 V.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HEF4020B-Q100 14-stage binary counter Rev. 3 — 7 December 2021 Product data sheet 1. General description The HEF4020B is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 3) and is suitable for use in automotive applications. 2.