NPIC6C4894-Q100 Datasheet PDF (Power logic 12-bit shift register)

NPIC6C4894-Q100 - Power logic 12-bit shift register

Datasheet Summary

Description

The NPIC6C4894-Q100 is a 12-stage serial shift register.

It has a storage latch associated with each stage for strobing data from the serial input (D) to the parallel open-drain outputs (QP0 to QP11).

Data is shifted on positive-going clock (CP) transitions.

Features

Automotive product qualification in accordance with AEC-Q100 (Grade 1).
Specified from 40 C to +125 C.
Low RDSon.
12 Power EDNMOS transistor outputs of 100 mA continuous current.
250 mA current limit capability.
Output clamping voltage 33 V.
30 mJ avalanche energy capability.
Low power consumption.
Latch-up performance exceeds 100 mA per JESD 78 Class II level A.
ESD protection:.
HBM AEC-Q100-002 revision D class H2 exceeds 2500 V.

Datasheet Details

Part number	NPIC6C4894-Q100
Manufacturer	nexperia
File Size	943.94 KB
Description	Power logic 12-bit shift register
Datasheet	NPIC6C4894-Q100 Datasheet
Additional preview pages of the NPIC6C4894-Q100 datasheet.

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Full PDF Text Transcription

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NPIC6C4894-Q100 Power logic 12-bit shift register; open-drain outputs Rev. 1 — 17 April 2014 Product data sheet 1. General description The NPIC6C4894-Q100 is a 12-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input (D) to the parallel open-drain outputs (QP0 to QP11). Data is shifted on positive-going clock (CP) transitions. The data in each shift register stage is transferred to the storage register when the latch enable (LE) input is HIGH. Data in the storage register drives the gate of the output extended-drain NMOS transistor whenever the output enable input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers.

Published: Jul 29, 2019 |