The 74F113 is a Dual J-K negative edge-triggered flip-flops.
| Package | SOP |
|---|---|
| Operating Voltage | 5 V |
| Max Voltage (typical range) | 5.5 V |
| Min Voltage (typical range) | 4.5 V |
| Logic Function | D-Type, Flip-Flop, JK-Type |
| Clock Edge Trigger | Negative Edge |
| Length | 10.2 mm |
| Width | 5.3 mm |
| Part Number | 74F113 Datasheet |
|---|---|
| Manufacturer | NXP Semiconductors |
| Overview | The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outpu. individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level at the other inputs. A high level on the clock (CP) input enables the J and K inputs. |
| Part Number | 74F113 Datasheet |
|---|---|
| Description | Dual JK Negative Edge-Triggered Flip-Flop |
| Manufacturer | Fairchild Semiconductor |
| Overview | The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pu. ify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009473 74F113 Unit Loading/Fan Out U.L. Pin Names J1, J2, K1, K2 CP1, CP2 SD1, SD2 Q1, Q2, Q1, Q2 Data Inputs Clock Pulse . |
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