74LVC1G175-Q100 Datasheet and Specifications PDF

The 74LVC1G175-Q100 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master rese.

and benefits
* Automotive product qualification in accordance with AEC-Q100 (Grade 1)
* Specified from -40 °C to +85 °C and from -40 °C to +125 °C
* Wide supply voltage range from 1.65 V to 5.5 V
* High noise immunity
* Overvoltage tolerant inputs to 5.5 V
* ±24 mA output drive (VCC = 3.0 V)
* CMOS .

The 74LVC1G175-Q100 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master rese.

allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered d.