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74VHC125 Datasheet

The 74VHC125 is a QUAD BUS BUFFERS. Download the datasheet PDF and view key features and specifications below.

Part Number74VHC125
ManufacturerSTMicroelectronics
Overview The 74VHC125 is an advanced high-speed CMOS QUAD BUS BUFFERS fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The device requires the 3-STATE control input G to . 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Figure 1: Pin Connection And IEC Logic Symbols November 2004 Rev. 7 1/12 74VHC125 Figure 2: Input Equivalent Circuit Table 2: Pin Descrip.
Part Number74VHC125
DescriptionQuad buffer/line driver
ManufacturerNexperia
Overview The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74VHC125; 74VH. and benefits
* Balanced propagation delays
* All inputs have a Schmitt-trigger action
* Inputs accepts voltages higher than VCC
* Input levels:
* The 74VHC125 operates with CMOS logic levels
* The 74VHCT125 operates with TTL logic levels
* ESD protection:
* HBM JESD22-A114E exceeds 2000 V
* MM JESD2.
Part Number74VHC125
DescriptionQuad Buffer
ManufacturerFairchild Semiconductor
Overview The VHC125 contains four independent non-inverting buffers with 3-STATE outputs. It is an advanced highspeed CMOS device fabricated with silicon gate CMOS technology and achieves the high-speed operat.
* High Speed: tPD = 3.8ns (Typ.) at VCC = 5V
* Lower power dissipation: ICC = 4 µA (Max.) at TA = 25°C
* High noise immunity: VNIH = VNIL = 28% VCC (Min.)
* Power down protection is provided on all inputs
* Low noise: VOLP = 0.8V (Max.)
* Pin and function compatible with 74HC125 General Description.
Part Number74VHC125
DescriptionQuad buffer/line driver
ManufacturerNXP Semiconductors
Overview The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74VHC125; 74VH. I Balanced propagation delays I All inputs have a Schmitt-trigger action I Inputs accepts voltages higher than VCC I Input levels: N The 74VHC125 operates with CMOS logic levels N The 74VHCT125 operates with TTL logic levels I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exce.