IDT23S05 Datasheet and Specifications PDF

The IDT23S05 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming .

* Phase-Lock Loop Clock Distribution
* 10MHz to 133MHz operating frequency
* Distributes one clock input to one bank of five outputs
* Zero Input-Output Delay
* Output Skew < 250ps
* Low jitter <200 ps cycle-to-cycle
* IDT23S05-1 for Standard Drive
* IDT23S05-1H for High Drive
* No external RC netw.

The IDT23S05 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming.

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* Phase-Lock Loop Clock Distribution 10MHz to 133MHz operating frequency Distributes one clock input to one bank of five outputs Zero Input-Output Delay Output Skew < 250ps Low jitter <200 ps cycle-to-cycle IDT23S05-1 for Standard Drive IDT23S05-1H for High Drive No external.