IDT23S05T Datasheet | Renesas

IDT23S05T 2.5VZERODELAYCLOCKBUFFER,SPREADSPECTRUMPATIBLE MERCIALANDINDUSTRIALTEMPERATURERANGES 2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM PATIBLE Features : - Phase-Lock Loop Clock Distribution - 10MHz to 133MHz operating frequency - Distributes one clock input to one bank of five outputs - Zero Input-Output Delay - Output Skew < 250ps - Low jitter <200 ps cycle-to-cycle - No external RC network required - Operates at 2.5V VDD - Power down mode - Spread spectrum patible - Available in SOIC package NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 DESCRIPTION: The IDT23S05T is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the ining clock and the output clock, operable within the range of 10 to 133MHz. The IDT23S05T is an 8-pin version of the IDT23S09T. IDT23S05T accepts one reference input, and drives out five low skew clocks. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT23S05T enters power down. In this mode, the device will draw less than 12μA for mercial Temperature Range and and less than 25μA for Industrial temperature range, the outputs are tristated, and the PLL is not running, resulting in a significant reduction of power. The IDT23S05T is characterized for both Industrial and mercial operation. FUNCTIONAL BLOCK DIAGRAM REF 1 PLL Control Logic 8 CLKOUT 3 CLK1 2 CLK2 5 CLK3 7 CLK4 The IDT logo is a registered trademark of Integrated Device Technology,...