IDT23S05E Datasheet
IDT23S05E Datasheet (Integrated Device)
Integrated Device
FUNCTIONAL BLOCK DIAGRAM 8 CLKOUT REF 1 PLL Control Logic 3 CLK1 2 CLK2 5 7 CLK3 CLK4 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTR.
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* Phase-Lock Loop Clock Distribution 10MHz to 200MHz operating frequency Distributes one clock input to one bank of five outputs Zero Input-Output Delay Output Skew < 250ps Low jitter <200 ps cycle-to-cycle IDT23S05E-1 for Standard Drive IDT23S05E-1H for High Drive No extern.
IDT23S05E Datasheet (Renesas)
Renesas
The IDT23S05E is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming.
* Phase-Lock Loop Clock Distribution
* 10MHz to 200MHz operating frequency
* Distributes one clock input to one bank of five outputs
* Zero Input-Output Delay
* Output Skew < 250ps
* Low jitter <200 ps cycle-to-cycle
* IDT23S05E-1 for Standard Drive
* IDT23S05E-1H for High Drive
* No external RC ne.