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74LS27 datasheet

74LS27 datasheet

74LS27 Triple 3-input Positive NOR Gates

Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39.

Motorola

74LS273 - OCTAL D FLIP-FLOP

OCTAL D FLIP-FLOP WITH CLEAR The SN54 / 74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock a.
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Mitsubishi Electric Semiconductor

74LS273 - OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP

.
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Hitachi Semiconductor

74LS27 - Triple 3-input Positive NOR Gates

Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.
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National Semiconductor

DM74LS273 - 8-BIT REGISTER

.
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National Semiconductor

DM74LS279 - Quad S-R Latches

54LS279 DM54LS279 DM74LS279 Quad S-R Latches May 1989 54LS279 DM54LS279 DM74LS279 Quad S-R Latches General Description The ’LS279 consists of four .
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Renesas

HD74LS27 - Triple 3-input Positive NOR Gates

HD74LS27 Triple 3-input Positive NOR Gates Features • Ordering Information Part Name Package Type Package Code Package (Previous Code) Abbreviatio.
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Mitsubishi

74LS273P - M74LS273P

www.DataSheet4U.com www.DataSheet4U.com www.DataSheet4U.com www.DataSheet4U.com .
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Hitachi Semiconductor

74LS279 - Quadruple S-R Latches

19.20 20.00 Max 16 9 7.40 Max 6.30 Unit: mm 1 1.3 1.11 Max 8 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° Hit.
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Renesas

HD74LS273 - Octal D-type Positive-edge-triggered Flip-Flops

HD74LS273 Octal D-type Positive-edge-triggered Flip-Flops (with Clear) REJ03D0473–0300 Rev.3.00 Jul.15.2005 The HD74LS273, positive-edge-triggered f.
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Renesas

HD74LS279 - Quadruple S-R Latches

HD74LS279 Quadruple S-R Latches Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS2.
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ON Semiconductor

74LS273 - LOW POWER SCHOTTKY

SN74LS273 Octal D Flip-Flop with Clear The SN74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Cl.
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Hitachi Semiconductor

74LS273 - Octal D-type Positive-edge-triggered Flip-Flops

Unit: mm 24.50 25.40 Max 20 11 7.00 Max 6.30 1 0.89 1.27 Max 10 1.30 2.54 Min 5.08 Max 7.62 0.51 Min 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15.
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National Semiconductor

74LS273 - 8-Bit Register

DM54LS273 DM74LS273 8-Bit Register with Clear April 1992 DM54LS273 DM74LS273 8-Bit Register with Clear General Description The ’LS273 is a high spee.
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Fairchild Semiconductor

74LS279 - Quad S-R Latch

DM74LS279 Quad S-R Latch August 1986 Revised March 2000 DM74LS279 Quad S-R Latch General Description The DM74LS279 consists of four individual and i.
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Motorola

SN74LS27 - TRIPLE 3-INPUT NOR GATE

TRIPLE 3-INPUT NOR GATE SN54/74LS27 VCC 14 13 12 11 10 9 8 TRIPLE 3-INPUT NOR GATE LOW POWER SCHOTTKY 1234567 GND GUARANTEED OPERATING RANGES .
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Texas Instruments

SN74LS273 - OCTAL D-TYPE FLIP-FLOP

• Contains Eight Flip-Flops With Single-Rail Outputs • Buffered Clock and Direct Clear Inputs • Individual Data Input to Each Flip-Flop • Applications.
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Texas Instruments

SN74LS279A - QUADRUPLE S-R LATCHES

SN54279, SN54LS279A, SN74279, SN74LS279A QUADRUPLE S-R LATCHES SDLS093 – DECEMBER 1983 – REVISED MARCH 1988 PRODUCTION DATA information is current as.
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National Semiconductor

74LS279 - Quad S-R Latches

54LS279 DM54LS279 DM74LS279 Quad S-R Latches May 1989 54LS279 DM54LS279 DM74LS279 Quad S-R Latches General Description The ’LS279 consists of four .
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Motorola

SN74LS279 - QUAD SET-RESET LATCH

SN54/74LS279 QUAD SET-RESET LATCH VCC 16 S1 15 R 14 Q 13 S1 12 S2 11 R 10 Q 9 QUAD SET-RESET LATCH LOW POWER SCHOTTKY 1 R 2 S1 3 S2 4 Q .
1.0 · rating-1
Hitachi Semiconductor

HD74LS27 - Triple 3-input Positive NOR Gates

Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.
1.0 · rating-1
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