SN74LS10N Datasheet | Specifications & PDF Download

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DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output

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SN74LS10 TRIPLE 3-INPUT NAND GATE VCC 14 13 12 11 10 9 8 1234567 GND Symbol VCC Supply Voltage Parameter TA Operating Ambient Temperature Ra

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SN74LS109A Dual JK Positive Edge−Triggered Flip−Flop The SN74LS109A consists of two high speed completely independent transition clocked JK flip-flops

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SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop The SN74LS109A consists of two high speed completely independent transition clocked JK flip-flops

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DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The c

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SN54107, SN54LS107A, SN74107, SN74LS107A DUAL J-K FLIP-FLOPS WITH CLEAR SDLS036 – DECEMBER 1983 – REVISED MARCH 1988 PRODUCTION DATA information is c

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SN5410, SN54LS10, SN54S10, SN7410, SN74LS10, SN74S10 TRIPLE 3-INPUT POSITIVE-NAND GATES SDLS035A – DECEMBER 1983 – REVISED APRIL 2003 PRODUCTION DATA

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PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device JM38510/30109BEA Status Package Type Package Pins Package

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