Datasheet4U Logo Datasheet4U.com

SN74LS109A Datasheet - Motorola

SN74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together. LOGIC DIAGRAM SET (SD) 5(11) CLEAR (CD) 1(15) CLOCK 4(12) J 2(14) K 3(13) Q 6(10) Q 7(9) MODE SELECT TRUTH TABLE OPERATING MODE INPUTS SD CD J OUTPUTS KQQ Set.

SN74LS109A Datasheet (147.54 KB)

Preview of SN74LS109A PDF
SN74LS109A Datasheet Preview Page 2 SN74LS109A Datasheet Preview Page 3

Datasheet Details

Part number:

SN74LS109A

Manufacturer:

Motorola

File Size:

147.54 KB

Description:

Dual jk positive edge-triggered flip-flop.

📁 Related Datasheet

SN74LS109 LOW POWER SCHOTTKY (ON Semiconductor)

SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop (ON Semiconductor)

SN74LS109A Dual J-K Positive-Edge-Triggered Flip-Flops (Texas Instruments)

SN74LS10 TRIPLE 3-INPUT NAND GATE (Motorola)

SN74LS10 TRIPLE 3-INPUT POSITIVE-NAND GATES (Texas Instruments)

SN74LS10 TRIPLE 3-INPUT NAND GATE (ON Semiconductor)

SN74LS107A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP (Motorola)

SN74LS107A DUAL J-K FLIP-FLOPS (Texas Instruments)

TAGS

SN74LS109A DUAL POSITIVE EDGE-TRIGGERED FLIP-FLOP Motorola

SN74LS109A Distributor