SN74LS114A Datasheet - Motorola

SN74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up times are observed. Input data is tra.

SN74LS114A Datasheet (111.41 KB)