Part Number | Description | Manufacture |
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(IS42S8800x/ IS42S16400x) 2M x 8-Bit x 4-Bank SDRAM h DESCRIPTION S The IS42S8800 and IS42S16400 are high-speed 67, Single 3.3V a (± 0.3V) power supply t 108,864-bit synchronous dynamic random-access High speed clock cycle time -7: 133MHz3-3-3, a moeories, organized as 2,097,152 x 8 x 4 and 1,04 |
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IS42S16100 • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks can be operated simultaneously and independently • Dual internal bank controlled by A11 (bank select) • Single 3.3V power suppl |
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SYNCHRONOUS DYNAMIC RAM • Clock frequency: 200, 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single 3.3V power supply • LVTTL interface • Programmable burst length – (1, 2, 4, 8, ful |
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SYNCHRONOUS DYNAMIC RAM • Clock frequency: 166, 133, 100 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single 3.3V power supply • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full pag |
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1M-Bit x 16-Bit 4 4-Bank SDRAM OVERVIEW t a ISSI's 64Mb Synchronous DRAM IS42S16400C1 is • Clock frequency: 166, 143 MHz D organized as 1,048,576 bits x 16-bit x 4-bank for improved . synchronous; all signals referenced to a • Fully performance. The synchronous DRAMs achieve high- |
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256Mb SYNCHRONOUS DRAM • Clock frequency: 200,166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, |
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512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM • Clock frequency: 166, 143, 100 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks can be operated simultaneously and independently • Dual internal bank controlled by A11 (bank select) • Single 3.3V power supply • L |
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256Mb SYNCHRONOUS DRAM • Clock frequency: 200, 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4 |
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512Mb SDRAM • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq |
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1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM • Clock frequency: 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single 3.3V power supply • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • |
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Total 36 results |