IDCI3 - CMOS Gate Array

AMI

General Description

IDCI3 is an inverting, CMOS-level input buffer piece.

IDCI3 cmos gate array by AMI - Datasheet Preview

Datasheet Details

Part number	IDCI3
Manufacturer	AMI
File Size	17.62 KB
Description	CMOS Gate Array
Datasheet	IDCI3 Datasheet

Full PDF Text Transcription for IDCI3 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for IDCI3. For precise diagrams, and layout, please refer to the original PDF.

,'&, ® $0,+* PLFURQ &026 *DWH $UUD Description IDCI3 is an inverting, CMOS-level input buffer piece. Logic Symbol Truth Table Pin Loading IDCI3 QC P PADM D PADM QC ...

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piece. Logic Symbol Truth Table Pin Loading IDCI3 QC P PADM D PADM QC LH HL Load PADM 4.90 pF HDL Syntax Verilog .................... IDCI3 inst_name (QC, PADM); VHDL...................... inst_name: IDCI3 port map (QC, PADM); Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 12.7 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Delay (ns) From To Parameter 1 PADM QC tPLH tPHL 0.62 0.72 Delay will vary with input conditions. See page 2-17 for interconnect estimates. Number of Equivalent Loads 11 22 32 0.76 0.85 0.92 0.87 0.98 1.06

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