Datasheet Summary
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Preliminary
Document Title 1M X 32 Bit X 4 Banks Synchronous DRAM Revision History
Rev. No.
1M X 32 Bit X 4 Banks Synchronous DRAM
History
Initial issue
Issue Date
January 13, 2005
Remark
Preliminary
PRELIMINARY
(January, 2005, Version 0.0)
AMIC Technology, Corp.
Preliminary
Features
JEDEC standard 3.3V power supply LVTTL patible with multiplexed address Four banks / Pulse RAS MRS cycle with address key programs
- CAS Latency (2,3)
- Burst Length (1,2,4,8 & full page)
- Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Deep Power Down Mode Burst Read Single-bit Write operation...