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A67P06181 - (A67P06181 / A67P93361) Flow-through ZeBL SRAM

Download the A67P06181 datasheet PDF. This datasheet also covers the A67P93361 variant, as both devices belong to the same (a67p06181 / a67p93361) flow-through zebl sram family and are provided as variant models within a single manufacturer datasheet.

Description

The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.

The A67P06181, A67P93361 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter.

Features

  • Fast access time: 6.5/7.5/8.5 ns (153, 133, 117 MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +2.5V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signals Registered output for pipelined.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (A67P93361_AMICTechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number A67P06181
Manufacturer AMIC Technology
File Size 269.79 KB
Description (A67P06181 / A67P93361) Flow-through ZeBL SRAM
Datasheet download datasheet A67P06181 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com A67P06181/A67P93361 Series Preliminary Document Title 1M X 18, 512K X 36 LVTTL, Flow-through ZeBLTM SRAM Revision History Rev. No. 0.0 1M X 18, 512K X 36 LVTTL, Flow-through ZeBLTM SRAM History Initial issue Issue Date September, 20, 2004 Remark Preliminary PRELIMINARY (September, 2004, Version 0.0) AMIC Technology, Corp. A67P06181/A67P93361 Series Preliminary Features Fast access time: 6.5/7.5/8.5 ns (153, 133, 117 MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +2.
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