89C51CC01 Key Features
- 80C51 Core Architecture 256 Bytes of On-chip RAM 1K Bytes of On-chip ERAM 32K Bytes of On-chip Flash Memory
- PWM (8-bit)
- High-speed Output
- Timer and Edge Capture Double Data Pointer 21-bit WatchDog Timer (7 Programmable Bits) A 10-bit Resolution Analog to Dig
- Fully pliant with CAN Rev2.0A and 2.0B
- Optimized Structure for munication Management (Via SFR)
- 15 Independent Message Objects
- Each Message Object Programmable on Transmission or Reception
- Individual Tag and Mask Filters up to 29-bit Identifier/Channel
- 8-byte Cyclic Data Register (FIFO)/Message Object