5270 Datasheet | Aeroflex Circuit Technology

ACT5270 64-Bit Superscaler Microprocessor Features s s Full militarized QED RM5270 microprocessor Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle q 133, s Integrated secondary cache controller (R5000 patible) q Supports 512K or 2MByte block write-through secondary s 150, 200 MHz operating frequencies - Consult Factory for latest speeds q 260 Dhrystone2.1 MIPS q SPECInt95 5.0, SPECfp95 5.3 s High-performance floating point unit q Single High performance system interface patible with RM5260, R4600, R4700 and R5000 q 64-bit cycle repeat rate for mon single precision operations and some double precision operations q Two cycle repeat rate for double precision multiply and double precision bined multiply-add operations q Single cycle repeat rate for single precision bined multiplyadd operation s multiplexed system address/data bus for optimum price/ performance with up to 100 MHz operating frequency q High performance write protocols maximize uncached write bandwidth q Supports clock divisors (2, 3, 4, 5, 6, 7, 8) q 5V patible I/O’s q IEEE 1149.1 JTAG boundary scan s MIPS IV instruction set q Floating point multiply-add instruction increases performance in signal processing and graphics applications q Conditional moves to reduce branch frequency q Index address modes (register + register) s Embedded application enhancements q Specialized Integrated on-chip caches q 16KB q 16KB instruction - 2 way set associative data - 2 way set associative q Virtually indexed, physically tagged q Write-back and write-through on per page basis q Pipeline restart on first double for data cache misses s DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction q I and D cache locking by set q Optional dedicated exception vector for interrupts s Fully static CMOS design with power down logic q Standby q6 reduced power mode with WAIT instruction Watts typical at 3.3V 200...