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AS4C1M16E5 - 5V 1M x 16 CMOS DRAM

Description

Address inputs Row address strobe Input/output Output enable Write enable Column address strobe, upper byte Column address strobe, lower byte Symbol tRAC tAA tCAC tOEA tRC tHPC ICC1 ICC5 -45 45 23 10 12 75 20 155 2.0 -50 50 25 12 13 80 20 145 2.0 -60 60 30 15 15 100 Unit ns ns ns ns ns mA mA

Features

  • hyper page mode operation where read and write operations within a single row (or page) can be executed at very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling edge of RAS and xCAS inputs, respectively. Also, RAS is used to make the column address latch transparent, enabling.

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Datasheet Details

Part number AS4C1M16E5
Manufacturer Alliance Semiconductor
File Size 635.37 KB
Description 5V 1M x 16 CMOS DRAM
Datasheet download datasheet AS4C1M16E5 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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$XJXVW  Š $6&0( 9 0î &026 '5$0 ('2 )HDWXUHV • Organization: 1,048,576 words × 16 bits • High speed - 45/50/60 ns RAS access time - 20/20/25 ns hyper page cycle time - 10/12/15 ns CAS access time • 1024 refresh cycles, 16 ms refresh interval - RAS-only or CAS-before-RAS refresh Read-modify-write • TTL-compatible, three-state DQ • JEDEC standard package and pinout - 400 mil, 42-pin SOJ - 400 mil, 44/50-pin TSOP 2 • Low power consumption - Active: 740 mW max (AS4C1M16E5-60) - Standby: 5.
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