AS7C33128NTF18B - 3.3V 128K x 18 Flowthrough Synchronous SRAM
Description
The AS7C33128NTF18B family is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM) organized as 131,072 words × 18 bits and incorporates a LATE Write.
Features
Organization: 131,072 words × 18 bits NTD™ architecture for efficient bus operation Fast clock to data access: 7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous operation Flow-through mode Asynchronous output enable control Available in 100-pin TQFP package.
Byte write enables Clock enable for operation hold Multiple chip e.
AS7C33128FT18B- 3.3V 128K x 18 Flow Through Synchronous SRAM
AS7C33128FT32B- (AS7C33128FT32B / AS7C33128FT36B) 3.3V 128K x 32/36 Flow Through Synchronous SRAM
AS7C33128FT36B- (AS7C33128FT32B / AS7C33128FT36B) 3.3V 128K x 32/36 Flow Through Synchronous SRAM
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April 2005
®
AS7C33128NTF18B
3.3V 128K x 18 Flowthrough Synchronous SRAM with NTDTM
Features
• • • • • • • • Organization: 131,072 words × 18 bits NTD™ architecture for efficient bus operation Fast clock to data access: 7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous operation Flow-through mode Asynchronous output enable control Available in 100-pin TQFP package • • • • • • • • Byte write enables Clock enable for operation hold Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation
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AS7C33128NTF18B Datasheet
