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Alliance Semiconductor Corporation

AS7C33128PFS32B Datasheet Preview

AS7C33128PFS32B Datasheet

(AS7C33128PFS32B / AS7C33128PFS36B) 3.3V 128K X 32/36 pipeline burst synchronous SRAM

No Preview Available !

March 2002
AS7C33128PFS32A
AS7C33128PFS36A
®
3.3V 128K X 32/36 pipeline burst synchronous SRAM
Features
• Organization: 131,072 words × 32 or 36 bits
• Fast clock speeds to 200 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns
• Fast OE access time: 3.0/3.1/3.5/4.0/5.0 ns
• Fully synchronous register-to-register operation
• Single register “Flow-through” mode
• Single-cycle deselect
www.DataSheet4DUu.caolm-cycle deselect also available (AS7C33128PFD32A/
AS7C33128PFD36A)
• Pentium®1 compatible architecture and timing
• Asynchronous output enable control
• Economical 100-pin TQFP package
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3 core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• 30 mW typical standby power in power down mode
• NTD™1 pipeline architecture available
(AS7C33128NTD32A/ AS7C33128NTD36A)
1 Pentium® is a registered trademark of Intel Corporation. NTD™ is a
trademark of Alliance Semiconductor Corporation. All trademarks
mentioned in this document are the property of their respective owners.
Logic block diagram
Pin arrangement
CLK
ADV
ADSC
ADSP
A[16:0]
GWE
BWE
BWd
BWc
BWb
BWa
CE0
CE1
CE2
ZZ
OE
LBO
CLK
CE
Q0
Burst logic
CLR
17 D
Q1 128K × 32/36
Q 17 15 17
Memory
array
CE
Address
register
CLK
D DQd Q
Byte write
registers
CLK
D DQc Q
Byte write
registers
CLK
D DQb Q
Byte write
registers
CLK
D DQa Q
Byte write
registers
CLK
36/32
36/32
4
Power
down
DQ
Enable
CE register
CLK
D Enable Q
delay
register
CLK
OE
Output
registers
CLK
Input
registers
CLK
36/32
FT DQ [a:d]
DQPc/NC
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
FT
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd/NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TQFP 14 × 20 mm
80 DQPb/NC
79 DQb
78 DQb
77 VDDQ
76 VSSQ
75 DQb
74 DQb
73 DQb
72 DQb
71 VSSQ
70 VDDQ
69 DQb
68 DQb
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSSQ
59 DQa
58 DQa
57 DQa
56 DQa
55 VSSQ
54 VDDQ
53 DQa
52 DQa
51 DQPa/NC
Note: Pins 1,30,51,80 are NC for ×32
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
–200
5
200
3
570
160
30
–183
5.4
183
3.1
540
140
30
–166
6
166
3.5
475
130
30
–133
7.5
133
4
425
100
30
–100
10
100
5
325
90
30
Units
ns
MHz
ns
mA
mA
mA
3/4/02; v.1.4
Alliance Semiconductor
P. 1 of 13
Copyright © Alliance Semiconductor. All rights reserved.




Alliance Semiconductor Corporation

AS7C33128PFS32B Datasheet Preview

AS7C33128PFS32B Datasheet

(AS7C33128PFS32B / AS7C33128PFS36B) 3.3V 128K X 32/36 pipeline burst synchronous SRAM

No Preview Available !

AS7C33128PFS32A
AS7C33128PFS36A
®
Functional description
The AS7C33128PFS32A and AS7C33128PFS36A are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 131,072 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given
technology.
Timing for these devices is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP
(TMS320C6X), and PowerPC1-based systems in computing, datacom, instrumentation, and telecommunications systems.
Fast cycle times of 5.0/5.4/6.0/7.5/10 ns with clock access times (tCD) of 3.0/3.1/3.5/4.0/5.0 ns enable 200, 183, 166, 133 and 100 MHz
bus frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller
address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst
addresses.
www.DataSheet4U.com
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed
by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the
output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent
clock edges. Address is incremented internally for the next access of the burst when ADV is sampled Low, and both address strobes are High.
Burst mode is selectable with the LBO input. With LBO unconnected or driven High, burst operations use a Pentium® count sequence. With
LBO driven LOW, the device uses a linear count sequence suitable for PowerPCand many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/
36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are disabled when BWn
is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low. Address is incremented internally to
the next burst address if BWn and ADV are sampled Low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).
• Master chip enable CE0 blocks ADSP, but not ADSC.
AS7C33128PFS32A and AS7C33128PFS36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate
at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package.
Capacitance
Parameter
Symbol
Signals
Test conditions
Max Unit
Input capacitance
CIN
Address and control pins
I/O capacitance
CI/O
I/O pins
Write enable truth table (per byte)
VIN = 0V
VIN = VOUT = 0V
5 pF
7 pF
GWE
L
H
H
H
BWE
X
L
H
L
BWn
X
L
X
H
WEn
T
T
F*
F*
.H\ X = Don’t Care, L = Low, H = High, T = True, F = False; *= Valid read; n = a, b, c, d; WE, WEn = internal write signal.
Burst Order
Interleaved Burst Order
LBO=1
Starting Address 00 01 10 11
First increment 01 00 11 10
Second increment 10 11 00 01
Third increment 11 10 01 00
Starting Address
First increment
Second increment
Third increment
Linear Burst Order
LBO=0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
1 PowerPCis a trademark International Business Machines Corporation.
3/4/02; v.1.4
Alliance Semiconductor
P. 2 of 13


Part Number AS7C33128PFS32B
Description (AS7C33128PFS32B / AS7C33128PFS36B) 3.3V 128K X 32/36 pipeline burst synchronous SRAM
Maker Alliance Semiconductor Corporation
Total Page 13 Pages
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1 AS7C33128PFS32A (AS7C33128PFS32A / AS7C33128PFS36A) 3.3V 128K X 32/36 pipeline burst synchronous SRAM
Alliance Semiconductor Corporation
2 AS7C33128PFS32B (AS7C33128PFS32B / AS7C33128PFS36B) 3.3V 128K X 32/36 pipeline burst synchronous SRAM
Alliance Semiconductor Corporation





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