AS7C33128PFD18B Datasheet | Alliance Semiconductor Corporation

Features - Organization: 131,072 words × 18 bits - Fast clock speeds to 200 MHz - Fast clock to data access: 3.0/3.5/4.0 ns - Fast OE access time: 3.0/3.5/4.0 ns - Fully synchronous register-to-register operation - Double-cycle deselect - Asynchronous output enable control - Available in 100-pin TQFP package .. - Individual byte write and global write - - - - - - Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power-standby mon data inputs and data outputs Logic block diagram CLK ADV ADSC ADSP A[16:0] CLK CS CLR Burst logic 17 15 17 Q D CS Address 128K × 18 Memory array register GWE BWb BWE BWa CE0 CE1 CE2 D DQb Q CLK D DQa Q CLK D Byte Write registers Byte Write registers Enable register Q OE Input registers CE CLK ZZ Output registers Power down D Enable Q delay register CLK OE 18 DQ [a,b] Selection guide - 200 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 5 200 3.0 375 130 30 - 166 6 166 3.5 350 100 30 - 133 7.5 133 4 325 90 30 Units ns MHz ns m A m A m...