AS7C33128PFD36B Overview
February 2005 ® AS7C33128PFD32B AS7C33128PFD36B 3.3V 128K X 32/36 pipeline burst synchronous SRAM.
AS7C33128PFD36B Key Features
- Organization: 131,072 words × 32 or 36 bits
- Fast clock speeds to 200 MHz
- Fast clock to data access: 3.0/3.5/4.0 ns
- Fast OE access time: 3.0/3.5/4.0 ns
- Fully synchronous register-to-register operation
- Double-cycle deselect
- Asynchronous output enable control
- Available in 100-pin TQFP package
- Individual byte write and global write Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O
- Single Cycle Deselect Pipelined Burst Synchronous SRAM