AS7C33128PFS36B Key Features
- Organization: 131,072 words × 32 or 36 bits
- Fast clock speeds to 200 MHz in LVTTL/LVCMOS
- Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns
- Fast OE access time: 3.0/3.1/3.5/4.0/5.0 ns
- Fully synchronous register-to-register operation
- Single register “Flow-through” mode
- Single-cycle deselect
- Dual-cycle deselect also available (AS7C33128PFD32A/ .. AS7C33128PFD36A)
- Pentium®1 patible architecture and timing
- Asynchronous output enable control