AS7C33256PFS18A Key Features
- Organization: 262,144 words × 16 or 18 bits
- Fast clock speeds to 166 MHz in LVTTL/LVCMOS
- Fast clock to data access: 3.5/3.8/4.0/5.0 ns
- Fast OE access time: 3.5/3.8/4.0/5.0 ns
- Fully synchronous register-to-register operation
- Single-cycle deselect
- Dual-cycle deselect also available (AS7C33256PFD16A/ .. AS7C33256PFD18A)
- Pentium®- patible architecture and timing
- Asynchronous output enable control