AS7C33256PFS18B - 3.3V 256K X 18 pipeline burst synchronous SRAM
Alliance Semiconductor Corporation
General Description
The AS7C33256PFS18B is a high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) devices organized as 262,144 words × 18 bits and incorporate a pipeline for highest frequency on any given technology.
Key Features
Organization: 262,144 words × 18 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.0/3.5/4.0 ns Fast OE access time: 3.0/3.5/4.0 ns Fully synchronous register-to-register operation Single-cycle deselect Asynchronous output enable control Available in 100-pin TQFP package.
Individual byte write and global write Multiple chip enables for.
Full PDF Text Transcription for AS7C33256PFS18B (Reference)
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December 2004 ® AS7C33256PFS18B 3.3V 256K × 18 pipeline burst synchronous SRAM Features • • • • • • • • Organization: 262,144 words × 18 bits Fast clock speeds to 200 MHz...
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• • Organization: 262,144 words × 18 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.0/3.5/4.0 ns Fast OE access time: 3.0/3.5/4.0 ns Fully synchronous register-to-register operation Single-cycle deselect Asynchronous output enable control Available in 100-pin TQFP package • • • • • • • Individual byte write and global write Multiple chip enables for easy expansion Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ www.DataSheet4U.
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AS7C33256PFS18B Datasheet
