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AS7C33256PFD18B - 3.3V 256K x 18 pipeline burst synchronous SRAM

General Description

The AS7C33256PFD18B is a high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) devices organized as 262,144 words × 18 bits and incorporate a pipeline for highest frequency on any given technology.

Key Features

  • Organization: 262,144 words × 18 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.0/3.5/4.0 ns Fast OE access time: 3.0/3.5/4.0 ns Fully synchronous register-to-register operation Double-cycle deselect Asynchronous output enable control Available in 100-pin TQFP package.
  • Individual byte write and global write Multiple chip enables for.

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Datasheet Details

Part number AS7C33256PFD18B
Manufacturer Alliance Semiconductor Corporation
File Size 582.27 KB
Description 3.3V 256K x 18 pipeline burst synchronous SRAM
Datasheet download datasheet AS7C33256PFD18B Datasheet

More Datasheets from Alliance Semiconductor Corporation

Part Number Description
AS7C33256PFD32A (AS7C33256PFD32A / AS7C33256PFD36A) 3.3V 256K x 32/36 pipelined burst synchronous SRAM
AS7C33256PFD36A (AS7C33256PFD32A / AS7C33256PFD36A) 3.3V 256K x 32/36 pipelined burst synchronous SRAM
AS7C33256PFS16A (AS7C33256PFS16A / AS7C33256PFS18A) 3.3V 256K X 16/18 pipeline burst synchronous SRAM
AS7C33256PFS18A (AS7C33256PFS16A / AS7C33256PFS18A) 3.3V 256K X 16/18 pipeline burst synchronous SRAM
AS7C33256PFS18B 3.3V 256K X 18 pipeline burst synchronous SRAM
AS7C33256PFS32A (AS7C33256PFS32A / AS7C33256PFS36A) 3.3V 256K x 32/36 pipelined burst synchronous SRAM
AS7C33256PFS36A (AS7C33256PFS32A / AS7C33256PFS36A) 3.3V 256K x 32/36 pipelined burst synchronous SRAM
AS7C33256FT18B 3.3V 256K x 18 Flow Through Synchronous SRAM
AS7C33256FT32A (AS7C33256FT32A / AS7C33256FT36A) 3.3V 256K x 32/36 Flow-through synchronous SRAM
AS7C33256FT36A (AS7C33256FT32A / AS7C33256FT36A) 3.3V 256K x 32/36 Flow-through synchronous SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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February 2005 ® AS7C33256PFD18B 3.3V 256K × 18 pipeline burst synchronous SRAM Features • • • • • • • • Organization: 262,144 words × 18 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.0/3.5/4.0 ns Fast OE access time: 3.0/3.5/4.0 ns Fully synchronous register-to-register operation Double-cycle deselect Asynchronous output enable control Available in 100-pin TQFP package • • • • • • • Individual byte write and global write Multiple chip enables for easy expansion Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ www.DataSheet4U.