Datasheet4U Logo Datasheet4U.com

AS7C33256PFD36A - (AS7C33256PFD32A / AS7C33256PFD36A) 3.3V 256K x 32/36 pipelined burst synchronous SRAM

Download the AS7C33256PFD36A datasheet PDF. This datasheet also covers the AS7C33256PFD32A variant, as both devices belong to the same (as7c33256pfd32a / as7c33256pfd36a) 3.3v 256k x 32/36 pipelined burst synchronous sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The AS7C33256PFD32A and AS7C33256PFD36A are high-performance CMOS 8-Mbit Synchronous Static Random Access Memory (SRAM) devices organized as 262,144 words x 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given technology.

Key Features

  • Organization: 262,144 words x 32 or 36 bits Fast clock speeds to 166 MHz Fast clock to data access: 3.5/4.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous register-to-register operation Dual-cycle deselect Asynchronous output enable control Available in100-pin TQFP.
  • Individual byte write and global write Multiple chip enables for easy expansio.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AS7C33256PFD32A_AllianceSemiconductorCorporation.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number AS7C33256PFD36A
Manufacturer Alliance Semiconductor Corporation
File Size 573.75 KB
Description (AS7C33256PFD32A / AS7C33256PFD36A) 3.3V 256K x 32/36 pipelined burst synchronous SRAM
Datasheet download datasheet AS7C33256PFD36A Datasheet

Full PDF Text Transcription for AS7C33256PFD36A (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for AS7C33256PFD36A. For precise diagrams, and layout, please refer to the original PDF.

December 2004 ® AS7C33256PFD32A AS7C33256PFD36A 3.3V 256K × 32/36 pipelined burst synchronous SRAM Features • • • • • • • • Organization: 262,144 words x 32 or 36 bits Fa...

View more extracted text
eatures • • • • • • • • Organization: 262,144 words x 32 or 36 bits Fast clock speeds to 166 MHz Fast clock to data access: 3.5/4.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous register-to-register operation Dual-cycle deselect Asynchronous output enable control Available in100-pin TQFP • • • • • • • Individual byte write and global write Multiple chip enables for easy expansion Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ www.DataSheet4U.