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EP1C20 Datasheet Preview

EP1C20 Datasheet

FPGA

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April 2003, ver. 1.2
®
Cyclone
FPGA Family
Data Sheet
Introduction
Preliminary
Information
Features...
The CycloneTM field programmable gate array family is based on a 1.5-V,
0.13-µm, all-layer copper SRAM process, with densities up to 20,060 logic
elements (LEs) and up to 288 Kbits of RAM. With features like phase-
locked loops (PLLs) for clocking and a dedicated double data rate (DDR)
interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory
requirements, Cyclone devices are a cost-effective solution for data-path
applications. Cyclone devices support various I/O standards, including
LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,
32-bit peripheral component interconnect (PCI), for interfacing with and
supporting ASSP and ASIC devices. Altera also offers new low-cost serial
configuration devices to configure Cyclone devices.
2,910 to 20,060 LEs, see Table 1
Up to 294,912 RAM bits (36,864 bytes)
Supports configuration through low-cost serial configuration device
Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
Support for 66-MHz, 32-bit PCI standard
Low speed (311 Mbps) LVDS I/O support
Up to two PLLs per device provide clock multiplication and phase
shifting
Up to eight global clock lines with six clock resources available per
logic array block (LAB) row
Support for external memory, including DDR SDRAM (133 MHz),
FCRAM, and single data rate (SDR) SDRAM
Support for multiple intellectual property (IP) cores, including
AlteraMegaCorefunctions and Altera Megafunctions Partners
Program (AMPPSM) megafunctions
Table 1. Cyclone Device Features
Feature
EP1C3
LEs
M4K RAM blocks (128 × 36 bits)
Total RAM bits
PLLs
Maximum user I/O pins (1)
2,910
13
59,904
1
104
Note to Table 1:
(1) This parameter includes global clock pins.
EP1C4
4,000
17
78,336
2
301
EP1C6
5,980
20
92,160
2
185
EP1C12
12,060
52
239,616
2
249
EP1C20
20,060
64
294,912
2
301
Altera Corporation
DS-CYCLONE-1.2
1




Altera

EP1C20 Datasheet Preview

EP1C20 Datasheet

FPGA

No Preview Available !

Cyclone FPGA Family Data Sheet
Preliminary Information
Cyclone devices are available in quad flat pack (QFP) and space-saving
FineLine BGApackages (see Tables 2 through 3).
Table 2. Cyclone Package Options & I/O Pin Counts
Device
100-Pin
TQFP (1)
144-Pin
TQFP (1), (2)
240-Pin
PQFP (1)
256-Pin
FineLine
BGA
324-Pin
FineLine
BGA
400-Pin
FineLine
BGA
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
65
104
249 301
98 185 185
173 185 249
233 301
Notes to Table 2:
(1) TQFP: thin quad flat pack.
PQFP: plastic quad flat pack.
(2) Cyclone devices support vertical migration within the same package (i.e., designers can migrate between the EP1C3
device in the 144-pin TQFP package and the EP1C6 device in the same package).
Table 3. Cyclone QFP & FineLine BGA Package Sizes
Dimension
100-Pin
TQFP
144-Pin
TQFP
240-Pin
PQFP
Pitch (mm)
Area (mm2)
Length × width
(mm × mm)
0.5
256
16 × 16
0.5
484
22 × 22
0.5
1,024
34.6 × 34.6
256-Pin
FineLine
BGA
1.0
289
17 × 17
324-Pin
FineLine
BGA
1.0
361
19 × 19
400-Pin
FineLine
BGA
1.0
441
21 × 21
2 Altera Corporation


Part Number EP1C20
Description FPGA
Maker Altera
Total Page 30 Pages
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