Altera Corporation May 2007 The Stratix® II FPGA family is based on a 1.2-V, 90-nm, all-layer copper SRAM process and features a new logic structure that maximizes perfo.

and has up to 96 DSP blocks with up to 384 (18-bit × 18-bit) multipliers for efficient implementation of high performanc.

EP2S

EP2S-3G1

EP2S-3G1T

EP2S-3G1TT

EP2S-3G2

EP2S-3G2T

EP2S-3G2TT

EP2S-3G3

EP2S-3G3T

EP2S-3G3TT

EP2S-3G4

EP2S-3G4T

EP2S-3G4TT