PA7572 Description
The PA7572 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on Anachip’s CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs. The PA7572 offers a versatile logic array architecture with 24 I/O pins, 14 input pins and 60 registers/latches (24...
PA7572 Key Features
- Independent or global clocks, resets, presets, clock polarity and output enables
- Sum-of-products logic for output enables Development and Programmer Support
- ICT PLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party programmers