Datasheet Details
| Part number | PA7572 |
|---|---|
| Manufacturer | Anachip |
| File Size | 349.21 KB |
| Description | Programmable Electrically Erasable Logic |
| Download | PA7572 Download (PDF) |
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| Part number | PA7572 |
|---|---|
| Manufacturer | Anachip |
| File Size | 349.21 KB |
| Description | Programmable Electrically Erasable Logic |
| Download | PA7572 Download (PDF) |
|
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The PA7572 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on Anachip’s CMOS EEPROM technology.
PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs.
The PA7572 offers a versatile logic array architecture with 24 I/O pins, 14 input pins and 60 registers/latches (24 buried logic cells, 12 input registers/latches, 24 buried I/O registers/latches).
PA7572 PEEL Array™ Programmable Electrically Erasable Logic Array Versatile Logic Array Architecture - 24 I/Os, 14 inputs, 60 registers/latches - Up to 72 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried High-Speed Commercial and Industrial Versions - As fast as 13ns/20ns (tpdi/tpdx), 66.6MHz (fMAX) - Industrial grade available for 4.5 to 5.5V VCC and -40 to +85 °C temperatures www.DataSheet4U.
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