PA7536 Datasheet - ICT

PA7536 Programmable Electrically Erasable Logic

The PA7536 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs. Th.

Commercial/Industrial PA7536 PEEL Array™ Programmable Electrically Erasable Logic Array Versatile Logic Array Architecture - 12 I/Os, 14 inputs, 36 registers/latches - Up to 36 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications - Integration of multiple PLDs and random logic - Buried counters, complex state-machines - Comparators, decoders, multiple.

PA7536 Features

* - Independent or global clocks, resets, presets, clock polarity and output enables - Sum-of-products logic for output enables Development and Programmer Support - ICT WinPLACE Development Software - Fitters for ABEL, CUPL and other software - Programming support by popular third-party programmer Ge

PA7536 Datasheet (215.55 KB)