PA7540 Datasheet - ETC

PA7540 PA7540 PEEL Array Programmable Electrically Erasable Logic

The PA7540 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs. The.

PA7540 PEEL Array™ Programmable Electrically Erasable Logic Array Most Powerful 24-pin PLD Available - 20 I/Os, 2 inputs/clocks, 40 registers/latches - 40 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications - Integration of multiple PLDs and random logic - Buried counters, complex state-machines - Comparators, decoders, multiplexers and other widegate .

PA7540 Features

* - Independent or global clocks, resets, presets, clock polarity and output enables - Sum-of-products logic for output enables Development and Programmer Support - Anachip’s WinPLACE Development Software - Fitters for ABEL, CUPL and other software - Programming support by popular third-party programm

PA7540 Datasheet (239.25 KB)