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ADN2865 Datasheet Clock and Data Recovery

Manufacturer: Analog Devices

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General Description

The ADN2865 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s.

An integrated deserialiser supports 8 bit parallel transfer to an FPGA or digital ASIC.

The recovered clock can simultaneously serialize data supplied in an 8 bit parallel format.

Overview

www.DataSheet4U.com Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery IC w/Loop Timed SERDES Preliminary Technical.

Key Features

  • Serial data input: 12.3 Mb/s to 2.7 Gb/s Exceeds ITU-T Jitter Specifications Integrated Limiting Amp: 6mV sensitivity Adjustable slice level: ±100 mV Patented dual-loop clock recovery architecture Programmable LOS detect and Slice Level Integrated PRBS Generator and Detector No reference clock required Loss of lock indicator Rate Selectivity without the use of a reference clock I2C™ interface to access optional features Single-supply operation: 3.3 V Low power: 1.0W 8 mm × 8 mm 56-lead LFCSP AD.

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