cmos ldo linear regulator.
Low noise: 11 μV rms independent of fixed output voltage PSRR of 88 dB at 10 kHz, 68 dB at 100 kHz, 50 dB at 1 MHz,
VOUT = 5 V, VIN = 7 V Input voltage range: 2.7 V to 20.
Regulation to noise sensitive applications ADC and DAC circuits, precision amplifiers, power for VCO VTUNE control
Commu.
The ADP7112 is a CMOS, low dropout (LDO) linear regulator that operates from 2.7 V to 20 V and provides up to 200 mA of output current. This high input voltage LDO is ideal for the regulation of high performance analog and mixed-signal circuits opera.
Image gallery
TAGS
Download (Size : 577.34KB)