900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Analog Devices Semiconductor Electronic Components Datasheet

ADRF5730 Datasheet

Silicon Digital Attenuator

No Preview Available !

Data Sheet
0.5 dB LSB, 6-Bit, Silicon Digital
Attenuator, 100 MHz to 40 GHz
ADRF5730
FEATURES
Ultrawideband frequency range: 100 MHz to 40 GHz
Attenuation range: 0.5 dB steps to 31.5 dB
Low insertion loss with impedance match
2.1 dB up to 18 GHz
2.9 dB up to 26 GHz
4.8 dB up to 40 GHz
Attenuation accuracy with impedance match
±(0.10 + 1.0% of attenuation state) up to 18 GHz
±(0.15 + 0.8% of attenuation state) up to 26 GHz
±(0.35 + 2.5% of attenuation state) up to 40 GHz
Typical step error with impedance match
±0.18 dB up to 18 GHz
±0.23 dB up to 26 GHz
±0.51 dB up to 40 GHz
High input linearity
P0.1dB insertion loss state: 30 dBm
P0.1dB other attenuation states: 27 dBm
IP3: 50 dBm typical
High RF input power handling: 27 dBm average, 30 dBm peak
Tight distribution in relative phase
No low frequency spurious signals
SPI and parallel mode control, CMOS/LVTTL compatible
RF settling time (0.1 dB of final RF output): 250 ns
24-terminal, 4 mm × 4 mm LGA package
Pin compatible with ADRF5720, low frequency cutoff version
APPLICATIONS
Industrial scanners
Test and instrumentation
Cellular infrastructure: 5G millimeter wave
Military radios, radars, electronic counter measures (ECMs)
Microwave radios and very small aperture terminals (VSATs)
GENERAL DESCRIPTION
The ADRF5730 is a silicon, 6-bit digital attenuator with 31.5 dB
attenuation control range in 0.5 dB steps.
This device operates from 100 MHz to 40 GHz with better than
4.8 dB of insertion loss and excellent attenuation accuracy. The
ADRF5730 has a radio frequency (RF) input power handling
capability of 27 dBm average and 30 dBm peak for all states.
The ADRF5730 requires a dual supply voltage of +3.3 V and
−3.3 V. The device features serial peripheral interface (SPI), parallel
mode control, and complementary metal-oxide semiconductor
(CMOS)-/low voltage transistor to transistor logic (LVTTL)-
compatible controls.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
FUNCTIONAL BLOCK DIAGRAM
LE
PS
GND
GND
ATTIN
GND
24 23 22 21 20 19
1
18
VDD
2
SERIAL/
17 VSS
PARALLEL
3
INTERFACE
16 GND
4
5
6
7
15 GND
6-BIT DIGITAL
ATTENUATOR
14
13
8 9 10 11 12
ATTOUT
GND
PACKAGE
BASE
GND
Figure 1.
The ADRF5730 is pin-compatible with the ADRF5720 low
frequency cutoff version, which operates from 9 kHz to 40 GHz.
The ADRF5730 RF ports are designed to match a characteristic
impedance of 50 Ω. For wideband applications, impedance
matching on the RF transmission lines can further optimize high
frequency insertion loss, return loss, and attenuation accuracy
characteristics. Refer to the Electrical Specifications section, the
Typical Performance Characteristics section, and the Applications
Information section for more details.
The ADRF5730 comes in a 24-terminal, 4 mm × 4 mm, RoHS-
compliant, land grid array (LGA) package and operates from
−40°C to +105°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2018–2020 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


Analog Devices Semiconductor Electronic Components Datasheet

ADRF5730 Datasheet

Silicon Digital Attenuator

No Preview Available !

ADRF5730
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
Power Derating Curves................................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Interface Schematics..................................................................... 7
Typical Performance Characteristics ............................................. 8
REVISION HISTORY
3/2020—Rev. 0 Rev. A
Changes to RF Power Parameter, Table 1 ...................................... 5
Changes to Table 3............................................................................ 6
Changes to Power Supply Section ................................................ 13
Added Power-Up State Section..................................................... 13
Moved Serial or Parallel Mode Selection Section and Table 7;
Renumbered Sequentially ......................................................................14
Data Sheet
Insertion Loss, Return Loss, State Error, Step Error, and
Relative Phase ................................................................................8
Input Power Compression and Third-Order Intercept......... 12
Theory of Operation ...................................................................... 13
Power Supply............................................................................... 13
RF Input and Output ................................................................. 13
Serial or Parallel Mode Selection ............................................. 14
Serial Mode Interface................................................................. 14
Parallel Mode Interface.............................................................. 15
Applications Information .............................................................. 16
Evaluation Board ........................................................................ 16
Probe Matrix Board ................................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
7/2018—Revision 0: Initial Version
Rev. A | Page 2 of 19


Part Number ADRF5730
Description Silicon Digital Attenuator
Maker Analog Devices
PDF Download

ADRF5730 Datasheet PDF






Similar Datasheet

1 ADRF5730 Silicon Digital Attenuator
Analog Devices
2 ADRF5731 Silicon Digital Attenuator
Analog Devices





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z



Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy