ADRV9040 Datasheet | Analog Devices

FEATURES Eight differential transmitters (Tx) Eight differential receivers (Rx) Two observation receivers (ORx) Single band and multiband (N x 2T2R/4T4R) capability 4 individual band profiles within tunable range1 Tunable range: 650 MHz to 6000 MHz 400 MHz i BW DPD support Ga N PA support via hardware accelerated, charge trapping correction algorithm Simplifying system thermal solution 13 W power consumption for all blocks enabled2 110°C maximum junction temperature, with operation up to 125°C3 Fully integrated DFE (DPD, CDUC, CDDC, CFR) engine that eliminates FPGAs and halves SERDES lane rate DPD adaptation engine for power amplifier linearization CDUC/CDDC- maximum 8 ponent carriers (CCs) per each Tx/Rx channel Multistage CFR engine Supports JESD204B/JESD204C digital interface Multichip phase synchronization for all LOs and baseband clocks Fully integrated fractional-N RF synthesizers Fully integrated clock synthesizer APPLICATIONS 3G/4G/5G TDD/FDD small cell, massive MIMO and macro base stations GENERAL DESCRIPTION The ADRV9040 is a highly integrated, system on chip (So C) radio frequency (RF) agile transceiver with integrated digital front end (DFE). The So C contains eight transmitters, two observation receivers for monitoring transmitter channels, eight receivers, integrated LO and clock synthesizers, and digital signal processing functions. The So C meets the high radio performance and low power consumption demanded by cellular infrastructure applications including small cell basestation radios, macro 3G/4G/5G systems, and massive MIMO base stations. The Rx and Tx signal paths use a zero-IF (ZIF) architecture that provides wide bandwidth with dynamic range suitable for contiguous and noncontiguous multicarrier base station applications. The ZIF architecture has the benefits of low power plus RF frequency and bandwidth agility. The lack of aliases and out-of-band images eliminates anti-aliasing and image filters. Rev. Pr A Document Feedback Information...