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Cypress Semiconductor Electronic Components Datasheet

CY23FP12 Datasheet

200MHz Field Programmable Zero Delay Buffer

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CY23FP12
200 MHz Field Programmable
Zero Delay Buffer
200 MHz Field Programmable Zero Delay Buffer
Features
Fully field-programmable
Input and output dividers
Inverting/non-inverting outputs
Phase-locked loop (PLL) or fanout buffer configuration
10 MHz to 200 MHz operating range
Split 2.5 V or 3.3 V outputs
Two LVCMOS reference inputs
Twelve low skew outputs
35 ps typical output-to-output skew (same frequency)
110 ps typical cycle-cycle jitter (same frequency)
Three-stateable outputs
Less than 50 A shutdown current
Spread aware
28-pin SSOP
3.3 V operation
Industrial temperature available
Functional Description
The CY23FP12 is a high performance fully field-programmable
200 MHz zero delay buffer designed for high speed clock
distribution. The integrated PLL is designed for low jitter and
optimized for noise rejection. These parameters are critical for
reference clock distribution in systems using high performance
ASICs and microprocessors.
The CY23FP12 is fully programmable through volume or
prototype programmers, enabling the user to define an
application-specific Zero Delay Buffer with customized input and
output dividers, feedback topology (internal/external), output
inversions, and output drive strengths. For additional flexibility,
the user can mix and match multiple functions listed in Table 2,
and assign a particular function set to any one of the four
possible S1-S2 control bit combinations. This feature enables
the implementation of four distinct personalities, selectable with
S1-S2 bits, on a single programmed silicon. The CY23FP12 also
features a proprietary auto power down circuit that shuts down
the device in case of a REF failure, resulting in less than 50 A
of current draw.
The CY23FP12 provides 12 outputs grouped in two banks with
separate power supply pins which can be connected
independently to either a 2.5 V or a 3.3 V rail.
Selectable reference input is a fault tolerance feature which
enables glitch-free switch over to a secondary clock source when
REFSEL is asserted/de-asserted.
For a complete list of related documentation, click here.
Logic Block Diagram
VDDC
Lock Detect
REFSEL
REF1
REFFB2K
M 100 to
400MHz
N PLL
1
2
3
4
X
S[2:1]
VSSC
Function
Selection
Test Logic
VDDA
CLKA0
CLKA1
CLKA2
CLKA3
CLKA4
CLKA5
VSSA
VDDB
CLKB0
CLKB1
CLKB2
CLKB3
CLKB4
CLKB5
VSSB
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07246 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 17, 2017


Cypress Semiconductor Electronic Components Datasheet

CY23FP12 Datasheet

200MHz Field Programmable Zero Delay Buffer

No Preview Available !

CY23FP12
Contents
Pin Configuration ............................................................. 3
Pin Description ................................................................. 4
Basic PLL Block Diagram ................................................ 5
Programmable Functions ................................................ 6
Field Programming the CY23FP12 ............................. 8
CyberClocksSoftware .............................................. 8
CY3672-USB Development Kit ................................... 8
CY23FP12 Frequency Calculation .................................. 8
Absolute Maximum Conditions ....................................... 9
Operating Conditions ....................................................... 9
DC Electrical Specifications .......................................... 10
Thermal Resistance ........................................................ 10
Switching Characteristics .............................................. 11
Switching Waveforms .................................................... 13
Test Circuits .................................................................... 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Drawing and Dimensions ............................... 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Document Number: 38-07246 Rev. *K
Page 2 of 19


Part Number CY23FP12
Description 200MHz Field Programmable Zero Delay Buffer
Maker Cypress
Total Page 19 Pages
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