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CY2DL1504 - 1:4 Differential LVDS Fanout Buffer

General Description

The CY2DL1504 is an ultra-low noise, low-skew, low-propagation delay 1:4 differential LVDS fanout buffer targeted to meet the requirements of high-speed clock distribution applications.

Key Features

  • Select one of two differential (LVPECL, LVDS, HCSL, or CML) input pairs to distribute to four LVDS output pairs.
  • Translates any single-ended input signal to 3.3 V LVDS levels with resistor bias on INx# input.
  • 30 ps maximum output-to-output skew.
  • 480 ps maximum propagation delay.
  • 0.11 ps maximum additive RMS phase jitter at 156.25 MHz (12 kHz to 20 MHz offset).
  • Up to 1.5 GHz operation.
  • Output enable and synchronous clock enable functions.
  • 20-pin TSSOP.

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📁 Similar Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input na1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Features ■ Select one of two differential (LVPECL, LVDS, HCSL, or CML) input pairs to distribute to four LVDS output pairs ■ Translates any single-ended input signal to 3.3 V LVDS levels with resistor bias on INx# input ■ 30 ps maximum output-to-output skew ■ 480 ps maximum propagation delay ■ 0.11 ps maximum additive RMS phase jitter at 156.25 MHz (12 kHz to 20 MHz offset) ■ Up to 1.5 GHz operation ■ Output enable and synchronous clock enable functions ■ 20-pin TSSOP ■ 2.5 V or 3.