CY2DL1504 Overview
The CY2DL1504 is an ultra-low noise, low-skew, low-propagation delay 1:4 differential LVDS fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DL1504 can select between two separate differential.
CY2DL1504 Key Features
- Select one of two differential (LVPECL, LVDS, HCSL, or CML) input pairs to distribute to four LVDS output pairs
- Translates any single-ended input signal to 3.3 V LVDS levels with resistor bias on INx# input
- 30 ps maximum output-to-output skew
- 480 ps maximum propagation delay
- 0.11 ps maximum additive RMS phase jitter at 156.25 MHz
- Up to 1.5 GHz operation
- Output enable and synchronous clock enable functions
- 20-pin TSSOP
- 2.5 V or 3.3 V operating voltage [1]
- mercial and industrial operating temperature range