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CY2DP1510 - 1:10 LVPECL Fanout Buffer

General Description

The CY2DP1510 is an ultra-low noise, low skew, low-propagation delay 1:10 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications.

Key Features

  • Select one of two differential (LVPECL, LVDS, HCSL, or CML) input pairs to distribute to 10 LVPECL output pairs.
  • Translates any single-ended input signal to 3.3 V LVPECL levels with resistor bias on INx# input.
  • 40-ps maximum output-to-output skew.
  • 600-ps maximum propagation delay.
  • 0.11-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset).
  • Up to 1.5-GHz operation.
  • 32-pin thin quad flat pack (TQFP) package.
  • 2.5-V or 3.3-V operating.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY2DP1510 1:10 LVPECL Fanout Buffer with Selectable Clock Input 1:10 LVPECL Fanout Buffer with Selectable Clock Input Features ■ Select one of two differential (LVPECL, LVDS, HCSL, or CML) input pairs to distribute to 10 LVPECL output pairs ■ Translates any single-ended input signal to 3.3 V LVPECL levels with resistor bias on INx# input ■ 40-ps maximum output-to-output skew ■ 600-ps maximum propagation delay ■ 0.11-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset) ■ Up to 1.5-GHz operation ■ 32-pin thin quad flat pack (TQFP) package ■ 2.5-V or 3.